Qualcomm Design rule development engineer in San Diego, California

Job Description:

Job Id E1957088

Job Title Design rule development engineer

Post Date 07/17/2017

Company-Division Qualcomm Technologies, Inc.

CDMA Technology at http://www.qualcomm.com/about/businesses/qct

Job Area Engineering - Manufacturing/Quality/Other

Engineering - Hardware

Location California - San Diego

Job Overview As a member of process technology team, this position will be responsible for evaluating design rules and fundamental circuit layouts, both custom and logic cell, as part of process tech teams foundry engagement activity for advanced nodes.

This position also works with the n+1 process tech team to implement new technology features, technology ground rules and design architectures in logic cell libraries for performance and scaling assessment. This role will also work on the pathfinding/defining design technology co-optimization (DTCO) to verify and evaluate new design rule/construct/cell architectures.


  • Primary responsibility is to evaluate/develop/define Front End of Line (FEOL), Middle of Line (MOL) and Back End of Line (BEOL) design rule for advanced nodes<=N7

  • Candidate will work closely with device and process integration engineers to align technology requirements, process assumptions and design rules to provide a unified technology definition.

  • Candidate will also work on evaluating/defining logic cell architecture for optimizing PPA and yield for advanced nodes.

  • Collaborate with cross functional teams to drive solutions to identified layout and process issues in meeting target PPA goal for N and N+1 technologies.

  • Figure of Merit (FOM) development/evaluation of design rules and logic cells identified from pathfinding activities

  • Work together with strategic technology team to identify roadmap and key technology elements in future integrations from design rule and cell architecture perspectives.

  • Technical reporting, documentation (patent, publication) and process transfer to internal technology enablement team.

Minimum Qualifications Minimum of 5 years of experience int the following areas:

  • Logic cell and design rule development.

  • Cell architecture expertise in advanced nodes

  • Working knowledge of FEOL and BEOL unit processes including Dielectric deposition, Lithography, Etch, PVD/CVD deposition, implant, CMP, etc.

  • Understanding of the process integration, design manual, and reliability.

  • Experience in optimizing CMOS process integration flow of advanced nodes for manufacturability and yield.

Preferred Qualifications - Excellent communication skills.

  • Demonstrated ability to meet deadlines and commitments.

Education Requirements M.S. or Ph.D. degree in Electrical/Materials Engineering, or related field.

EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.