Qualcomm IC Package RF/PMIC/Module Design Engineer in San Diego, California
Job Id E1957870
Job Title IC Package RF/PMIC/Module Design Engineer
Post Date 08/09/2017
Company-Division Qualcomm Technologies, Inc.
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
Job Area Engineering - Hardware
Location California - San Diego
Job Overview The IC Package Architecture Design team has an opening for a RF/PMIC SiP/Module Package Design Lead. This team is responsible for road mapping, architecting, design methodology, design implementation and verification for Qualcomm package products (Digital, RF, Analog, PMIC, etc...)
Job responsibilities for this position include package selection & package design. This involves optimizing system co-design of IC-PKG-PCB keeping in mind package footprint/height constraints, IC floor-planning, PCB, high-speed signal integrity, power distribution network and thermal constraints
7+ years of IC package design and layout experience
Package Design expertise in SIP/Module in 2-4+ layer laminate substrate technologies (BGA & LGA)
Package design flow methodology implementing RF & PMIC constrain, isolation, current distribution, and RLC spec.
Hands-on experience in package signal integrity SI/PI model creation, simulation, and design constrain implementation.
Knowledge of assembly and substrate manufacturing processes, package technology trade-off, design rules in wire bond, flip chip, and SiP/Module.
SIP/Module design verification & validation flow.
PCB level analysis affecting package array/pinout, PCB fanout, PCB stack-up, and analysis of de-cap placement (internal or external)
System level knowledge of mobile architecture and understanding of trade-offs made for partitioning of the key devices (Digital Baseband, Digital Apps Processor, RF, PA, PMIC, Audio, etc...)
Package level netlist capture and mechanical/electrical constraint management
Package level thermal performance and enhancement techniques
System level co-design methodology of IC, Package and PCB/Board
IC top level floor planning including RDL and bump pattern/assignment
Package pinout optimization incorporating system level trade-offs of pad/bump assignment, package routing and PCB target component pinouts
Experience in concept analysis for new product package selection based on requirements for mechanical, thermal and electrical performance with the goal to achieve lowest system level costSoftware:
Cadence SiP/APD (including Constraint Manager)
EM simulation tool (Ansys Q3D, HFSS or equivalent)
Understanding of package cost structure.
Design layout understanding of PCB breakout for mid to low tier mobile products (phones/tablets)
Understanding of package reliability requirements.
Tolerance Stack up analysis
Geometric Dimensioning and Tolerancing (GD&T) basic knowledgeSoftware:
Downstream Tech CAM350
Mentor Valor is a plus
Operating Systems: UNIX/Linux
Education Requirements Required: Bachelor's, Electrical Engineering and/or Mechanical Engineering
Preferred: Master's, Electrical Engineering and/or Mechanical Engineering
EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.